.Dd October 7, 2025
.Dt clarity 7
.Os https://cshort.io/
.Sh NAME
.Nm Clara Schaertl Short
.Nd eclectical engineer returning from sabbatical
.Sh SYNOPSIS
.Nm cu
.Fl c
.Qq +1 (310) 237-2826
.Nm mail
.Fl s
.Qq Your resume
clara@cshort.io
.Nm curl
https://cshort.io/clarity.7
|
.Cm mandoc
.Sh DESCRIPTION
Clara Short (they/them or she/her) is a hardware engineer who
.Em happens
to mostly write software these days: most recently, tools for bringing up,
validating, and using the new Design for Debug (DFD) features on the next
generation of phone and laptop SoCs.
In other words, they use their
training as an EE to make hardware debugging easier for software engineers.
Their favorite method of building trust with other teams is to start
submitting pull requests for features their own team needs.
.Pp
This year Clara took a short break to work on personal projects, and
semi-accidentally ended up turning one of them into a commercial product
(pending launch).
.Sh EXAMPLES
.Ss September 2025 - present: Owner, Autonoë Systems LLC, Medford, MA
.Bl -bullet -compact
.It
Designed a low-cost AMD UltraScale+ FPGA development board
with 28 Gbps expansion ports.
.It
Created demo workloads exercising PCI Express, 100 Gigabit Ethernet
and DDR4 SDRAM.
.It
Debugged signal integrity/power integrity issues on early revisions with
minimal lab tools.
.It
Released all design files as open-source hardware.
.It
Launching on Crowd Supply in winter 2025-26.
.El
.Ss July 2019 - April 2025: Silicon Validation Engineer, Apple Inc., Waltham, MA
.Bl -bullet -compact
.It
Responsible for silicon bringup and validation of Apple's cross-triggering
network on each SoC.
.It
Created tools to extract DFD architecture information directly from the
RTL design.
.It
Extended the OS kernel, boot loader, and SoC debugger to enable new
validation use cases.
.It
Trained triage engineers in tool usage and provided hands-on support
during bringup and debug.
.It
Led discussions with IP designers and software teams
about future requirements.
.El
.Ss May 2018 - August 2018: Silicon Validation Intern, Apple Inc., Austin, TX
.Bl -bullet -compact
.It
Wrote the collateral extraction tool for a new DFD feature,
saving 20 engineer-hours per stepping.
.It
Re-implemented SoC debugger support for the new feature to streamline
collateral delivery.
.El
.Ss June 2014 - December 2017: Control Systems Engineer, Mangan Inc., Long Beach, CA
.Bl -bullet -compact
.It
Designed and commissioned Programmable Logic Controller (PLC) systems in
oil refineries.
.It
Created the client's standard software library for process
analyzer PLCs.
.It
Introduced a tool for semi-automatic PLC software validation,
saving 80 engineer-hours per project.
.It
Independently managed projects up to $5,000.
.El
.Ss May 2009 - May 2014: Submarine Officer, United States Navy, Kings Bay, GA
.Bl -bullet -compact
.It
Shift supervisor for operations, maintenance, and testing of a
nuclear submarine with a crew of 160.
.It
Line manager for 12 electricians and electronics technicians.
.El
.Sh COMPATIBILITY
Clara works best in a collaborative environment, where there's a culture of
engineers regularly looking at each other's work and occasionally pairing
on tricky problems.
They prefer distributed, cross-functional organizations
where accountability is everywhere but
.Qq ownership
is a dirty word - see
above re: their habit of trading pull requests with other teams.
.Pp
Remote work is a hard requirement for Clara, but they are willing to travel
to the lab for hardware bringups (up to two weeks per quarter).
.Sh STANDARDS
.Bl -bullet -compact
.It
Fluent in Python and C.
.It
Conversational in C++,
.Xr Tcl n ,
.Xr sh 1 ,
and SystemVerilog.
.It
Proficient with AMD FPGA toolchains, JTAG, and IEEE 1500.
.El
.Sh HISTORY
.Ss August 2017 - May 2019: M.S. Electrical and Computer Engineering
University of Texas at Austin, Austin, TX.
.Ss June 2005 - May 2009: B.S. Electrical Engineering
United States Naval Academy, Annapolis, MD.