Hi, I’m Clara! I’m a hardware validation engineer working in Austin, Texas. At various other times, I’ve also been a grad student at UT Austin, a professional EE designing safety-critical control systems for oil refineries in Los Angeles, a submarine officer in the Navy, and—long, long ago—a weird little kid named [redacted] growing up in small-town upstate New York. Sometimes I take on projects for a certain awesome roboticist.
April 2019: I implemented the binary/BCD error checker proposed in , identified one design bug, and obtained the first available post-route area and delay figures  showing a much smaller area savings and performance penalty than predicted. The Verilog models are available online, including a Ladner-Fischer adder with 12% less area and only 4% greater delay than the equivalent DesignWare block.
August 2018: I put together a bibliography (LaTeX, PDF) with DOIs for about 90% of the papers in . Please let me know if you find a canonical URL for items 18, 26, or 37.
December 2017: I wrote a quick and dirty build script for the gem5 emulator, the SPEC CPU2006 benchmarks, and the SimPoint program phase analysis tool while reproducing part of  in my computer architecture class.
June 2017: I wrote a strategy guide/spoiler for TIS-100, because even video games about programming need language docs.
Unfortunately Fortunately, I started grad school two months later and suddenly found dozens of more urgent things to do.
June 2009: Just before software-defined radios smaller than a breadbox became widely available for under $1000, I made one for my undergraduate senior design project  using the then-newly released BeagleBoard as the host PC.
January 2019–May 2019: I moderated the Trans Thursdays drop-in discussion group at UT Austin’s Gender and Sexuality Center.
May 2018: I signed the Post-Meritocracy Manifesto, which reflects my beliefs about a healthy work environment.
March 2018: I wrote a response  to a small group of therapists who believe there is a “psychic epidemic” of gender dysphoria among people under age 25, despite the evidence that people who say they are transgender typically know what they mean by it.
December 2016: I signed the neveragain.tech pledge, which states in part: “We refuse to participate in the creation of databases of identifying information for the United States government to target individuals based on race, religion, or national origin.”
- A. Vázquez and E. Antelo, “A sum error detection scheme for decimal arithmetic,” ARITH 24, 2017, doi:10.1109/arith.2017.34.
- C. S. Short and E. E. Swartzlander, Jr., “Performance evaluation of a sum error detection scheme for decimal arithmetic,” to be presented at Asilomar 2019, preprint available.
- E. E. Swartzlander, Jr., ed., Computer arithmetic, vol. 1, 2015, doi:10.1142/9476.
- A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer, “High performance cache replacement using re-reference interval prediction (RRIP)” , ISCA 2010, doi:10.1145/1815961.1815971.
- C. R. Anderson, G. Schaertl, and P. Balister, “A low-cost embedded SDR solution for prototyping and experimentation,” tutorial at Wireless@VT 2009, paper in SDR 2009, source on GitHub.
- C. S. Short, “Comment on ‘Outbreak: on transgender teens and psychic epidemics,’” Psychological Perspectives, vol. 62, no. 2, 2019, in press, preprint available.